In order to achieve automotive grade quality, mixed analog and power products must pass a gate stress test. The purpose of the stress test is to screen random defects located in the gate oxide of the power MOS transistor. The stress test typically requires a dedicated test mode and test pad to control the gate of the MOS transistor.
A typical power product for automotive applications is a buck regulator with boot-strap having an NDMOS transistor as a high side power device. Such a buck regulator with the high side driver and test circuit pad is shown in FIG. 1.
The integrated circuit portion 102 of circuit 100 includes a driver stage 104 for driving the gate of the high side power MOS transistor MHS. The gate stress pad 106 is also coupled to the output of the driver stage 104 and the gate of the high side power MOS transistor MHS. The driver stage 104 is coupled between the BOOST node and the SBUCK node, and receives the HS input signal. The boost node is coupled to the V1 voltage input through diode D2. The drain of transistor MHS is coupled to the VIN node, and the source of transistor MHS is coupled to the SBUCK node. External to the integrated circuit portion 102, capacitor CB is coupled between the BOOST and SBUCK nodes and inductor L is coupled between the SBUCK and VOUT nodes. Diode D1 is coupled between the SBUCK node and ground. Capacitor COUT and resistor RLOAD are both coupled between the VOUT node and ground.
Referring now to FIG. 2, circuit 200 includes further transistor and gate levels of the driver circuit and gate stress test circuit. Driver stage 204, diode D2, gate stress pad 206, transistor MHS, and diode 208 correspond to similar elements in FIG. 1. The integrated circuit portion 202 includes further elements including inverter 210 for receiving the gate-stress test signal, inverter 212, OR gate 214, and AND gate 216. The integrated circuit portion 202 further includes transistors M1, M2, M3, M4, and parallel-connected diodes 218, 220, and 222. A resistor R1 is coupled between the gate and source of transistor M2.
In FIG. 2, transistor MHS is a high side NDMOS transistor, transistor M1 is a 3.3V PMOS transistor, transistor M2 is a high voltage PMOS transistor, and transistors M3 and M4 are high voltage NMOS transistors. As before, HS is the high side drive signal.
In the gate stress test mode, the gate-stress test signal is high, and transistors M1, M2, M3 and M4 are all off. The following steps are performed in the test mode:
A first step is the pre-stress leakage measurement. The VIN voltage is raised until the bias circuit and logic can work, forcing VIN=SBUCK, forcing the gate-stress pad voltage to be equal to VIN+normal VGS, and measuring current passing through the gate-stress pad.
A second step is to fully stress transistor MHS. The gate-stress pad voltage is raised to a VIN+stress voltage for a predetermined stress duration interval Ts.
A third step is performing a new leakage measurement. The gate-stress pad voltage is decreased to VIN+normal VG, and the current passing through the gate-stress pad is measured.
A fourth step is that a nonzero delta leakage is an indication of a possible gate failure.
As one example, a transistor oxide thickness is equal to 7 nm, a normal VGS is equal to 3.3V, a normal stress voltage is 6V, and a normal stress duration interval Ts is between 50 ms and 250 ms.
What is desired is a high side driver for a buck regulator, without a test pad, that will consume less die area, and has a driver stage design that is easy to use in a split power MOS application.